Engine Controls - Description & Operation (Except Diesel & Hybrid): Diagnosis Ford Escape I рестайлинг 2

DTC Structure

Like all digital signals, DTCs are sent to the scan tool as a series of 1s and 0s. Each DTC is made up of two data bytes which each consist of 8 bits that can be set to 1 or 0. The data is decoded by the scan tool to display each set of 4 bits as a hexadecimal number (0 to F) in order to display the DTCs in the conventional format. For example, P0420 - Catalyst System Efficiency Below Threshold (Bank 1).

DTC REFERENCE

The table below shows how to decode the bits into hex digits.

BINARY BIT PATTERN REFERENCE

The first 4 bits of a DTC do not convert directly into hex digits. The conversion into different types of DTCs (P, B, C and U) is defined by SAE J2012. This standard contains DTC definitions and formats.

BINARY BIT PATTERN REFERENCE

ISO 14229 sends two additional bytes of information with each DTC, a failure type byte and a status byte.

DTC REFERENCE

All ISO 14229 DTCs are 4 bytes long instead of 3 or 2 bytes long. Additionally, the status byte for ISO 14229 DTCs is defined differently than the status byte for previous applications with 3 byte DTCs.

DTC Status Bit Definitions

Refer to the following status bit descriptions

Bit 7

1. 0 - The ECU is not requesting warning indicator to be active
2. 1 - The ECU is requesting warning indicator to be active

Bit 6

1. 0 - The DTC test completed this monitoring cycle
2. 1 - The DTC test has not completed this monitoring cycle

Bit 5

1. 0 - The DTC test has not failed since last code clear
2. 1 - The DTC test failed at least once since last code clear

Bit 4

1. 0 - The DTC test completed since the last code clear
2. 1 - The DTC test has not completed since the last code clear

Bit 3

1. 0 - The DTC is not confirmed at the time of the request
2. 1 - The DTC is confirmed at the time of the request

Bit 2

1. 0 - The DTC test completed and was not failed on the current or previous monitoring cycle
2. 1 - The DTC test failed on the current or previous monitoring cycle

Bit 1

1. 0 - The DTC test has not failed on the current monitoring cycle
2. 1 - The DTC test failed on the current monitoring cycle

Bit 0

1. 0 - The DTC is not failed at the time of request
2. 1 - The DTC is failed at the time of request

For DTCs that illuminate the MIL, a confirmed DTC means the PCM has stored a DTC and has illuminated the MIL. If the fault has corrected itself, the MIL may no longer be illuminated but the DTC still shows a confirmed status for 40 warm up cycles at which time the DTC is erased.

For DTCs that do not illuminate the MIL, a confirmed DTC means the PCM has stored a DTC. If the fault has corrected itself, the DTC still shows a confirmed status for 40 warm up cycles at which time the DTC is erased.

To determine if a test has completed and passed, for example, after a repair, information can be combined from 2 bits as follows

If bit 6 is 0 (the DTC test completed this monitoring cycle), and bit 1 is 0 (the DTC test has not failed on the current monitoring cycle), then the DTC has been evaluated at least once this drive cycle and was a pass.

If bit 6 is 0 (the DTC test completed this monitoring cycle) and bit 0 is 0 (the DTC test is not failed at the time of request), then the most recent test result for that DTC was a pass.

The status byte bits can be decoded as a 2 digit hexadecimal number, and can be displayed as the last 2 digits of the DTC, for example for DTC P0110:1C-AF, AF represents the status byte info.

STATUS BYTE REFERENCE

Permanent Diagnostic Trouble Code (DTC)

The software stores a permanent DTC in non-volatile random access memory (NVRAM) whenever a DTC is set and the malfunction indicator lamp (MIL) has been illuminated. Permanent DTCs can only be cleared by the module strategy itself. After a permanent DTC is stored, three consecutive test passed monitoring cycles must complete before the permanent DTC can be erased. The PCM clears the permanent DTCs after one monitoring cycle if a request to clear DTCs is sent by the scan tool and the test subsequently runs and passes. A permanent DTC cannot be erased by clearing the keep alive memory (KAM). The intended use of the permanent DTC is to prevent vehicles from passing an in-use inspection simply by disconnecting the battery or clearing the DTCs with a scan tool prior to the inspection. The presence of the permanent DTCs at an inspection without the MIL illuminated is an indication that a correct repair was not verified by the onboard monitoring system.

Pressure Test Point

On some applications there is a pressure test point with a Schrader fitting in the fuel rail that relieves the fuel pressure and measures the fuel injector supply pressure for repair and diagnostic procedures. Before repairing or diagnosing the fuel system, read any WARNING information. On vehicles not equipped with a Schrader valve, use the Rotunda Fuel Pressure Test Kit 134-R0087 or equivalent.

Low Idle Air Flow Test

When the cold start emission reduction monitor is enabled, the powertrain control module (PCM) commands the idle air control system to increase the RPM, which elevates engine air flow. While this cold start emission reduction elevated air flow is requested, the low idle air flow test compares the measured idle air flow from the mass air flow (MAF) sensor to the commanded idle air control strategy. For the purpose of detecting low air flow concerns, the low air flow test uses the measured air flow and the commanded air flow to create a low air flow index.

Low idle air flow test entry conditions

1. Engine coolant temperature is between 4.4°C (40°F) and 82.2°C (180°F)
2. Barometric pressure is between 76.2 kPa (22.5 in-Hg) and 105 kPa (31 in-Hg)
3. Engine off soak time is at least 50 minutes
4. Throttle is at closed position

Spark Timing Monitor Test

The PCM is equipped with a spark conduction capture circuit which measures the timing and duration of the spark delivered by processing the flyback voltage signal from the primary side of the ignition coil. When the cold start emission reduction monitor is enabled, the spark control strategy in the PCM commands the spark timing strategy to retard the spark timing. While retarded spark timing is requested, the spark timing monitor compares the measured spark timing from the spark conduction capture circuit to the commanded spark timing from the spark control strategy. For the purpose of detecting spark timing failures, the spark timing monitor increments a fault filter if the measured spark timing is advanced by more than 5 degrees from the commanded spark timing. A failure is indicated if the fault filter exceeds a value of 200, equivalent to a failure duration of approximately 4 seconds.

Spark timing monitor test operation

1. DTC: P050B cold start ignition timing performance
2. Monitor execution: once per driving cycle, from start up with the cold start emission reduction monitor active
3. Monitor sequence: none
4. Monitoring duration: 7 seconds

Spark timing monitor test entry conditions

1. Engine speed is between 400 RPM and 2,000 RPM
2. Engine position and cylinder identification are synchronized
3. There are no concerns with the ignition coils primary circuits